Week 9: Digital Logic & Computer System Architecture

1. Number Systems & Boolean Circuits

Binary, octal, decimal and hexadecimal conversions are foundational and still directly tested. For negative numbers, two's complement is the standard representation: invert all bits and add 1 — its key advantage is that addition and subtraction use the same hardware circuit regardless of sign, and there is exactly one representation of zero (unlike one's complement or sign-magnitude, which have two).

Combinational circuits (output depends only on current inputs — adders, multiplexers, decoders) are designed by writing a truth table, deriving a Boolean expression (often minimised using Karnaugh maps), and implementing it with gates. Sequential circuits (output depends on current inputs AND past state, via memory elements like flip-flops) implement things like counters and registers — the SR, D, JK and T flip-flops are the standard set NTA expects you to know the characteristic equations for.

Step 1: write 13 in binary (8-bit):        0000 1101
Step 2: invert every bit (one's complement): 1111 0010
Step 3: add 1:                               1111 0011   <- this is -13

Check: adding +13 (0000 1101) and -13 (1111 0011) in 8-bit
two's complement gives 1 0000 0000 -> discard the overflow
carry bit -> 0000 0000, confirming the result is exactly 0.

2. CPU Architecture: Instruction Sets & Addressing Modes

A CPU executes an instruction through the fetch-decode-execute cycle: fetch the instruction from memory (using the Program Counter), decode it to determine the operation and operands, then execute it. Addressing modes determine how an operand's location is specified: immediate (value is embedded in the instruction), direct (address given directly), indirect (instruction holds the address of the address), and indexed/register-indirect (used heavily for arrays and loops).

RISC (Reduced Instruction Set Computer — few, simple, fixed-length instructions, more registers, relies on the compiler) is contrasted with CISC (Complex Instruction Set Computer — many, variable-length, more powerful instructions, e.g. classic x86) — RISC's simplicity is specifically what makes efficient pipelining easier, which is why the RISC/CISC distinction and pipelining are taught together.

3. Pipelining, Memory Hierarchy & I/O

Pipelining overlaps the execution of multiple instructions across stages (fetch, decode, execute, memory access, write-back) to increase throughput. Hazards break this overlap: structural hazards (two instructions need the same hardware resource simultaneously), data hazards (an instruction needs a result a previous instruction hasn't produced yet), and control hazards (a branch instruction means the next instruction to fetch isn't known yet).

The memory hierarchy — registers, cache (L1/L2/L3), main memory (RAM), secondary storage — trades capacity for speed at every level, exploiting the principle of locality of reference: temporal locality (recently accessed data is likely accessed again soon) and spatial locality (nearby data is likely accessed soon too) are exactly why caching works at all. I/O is handled via polling (CPU repeatedly checks device status — simple but wastes CPU cycles), interrupts (device signals the CPU when ready — efficient), and DMA (Direct Memory Access — device transfers data to/from memory without CPU involvement in the transfer itself, freeing the CPU for other work).

4. Hands-on Exercise

5. Exam-Style Practice (UGC NET Pattern)

Five NTA-pattern questions on number systems, circuits and CPU architecture.